THE 8051 ARCHITECTURE
ALU
Memory
Peripherals
Timing and control unit
Oscillator
ALU
Arithmetic and logic unit performs all arithmetic (addition,
subtraction, multiplication and division) and logical (AND,
OR, NOT, EXCLUSIVE-OR and rotating) operations on 8
bit data i.e. the 8051 has 8 bit ALU. The ALU also updates
information about the nature of the result in the flag
register (PSW).
Memory
The 8051 family has separate on-chip program and data
memory. The program instructions are stored in a
program memory. , 80C51 has 4Kbytes of on-chip ROM,
whereas 80C52 has 8Kbyte (ROM) , 87C51 has 4Kbytes
(EPROM) and 87C52 has 8Kbytes(EEPROM) of on-chip
program memory. Data memory can be on-chip or offchip. Internal data memory (RAM) in 80C51 is 128 bytes
and in 80C52 is 256 bytes.
Peripherals
The 8051 has two 16 bit timers (8052 has three timers)
that are used for timing and counting applications. It has
full duplex serial port (UART) to handle serial data
transmission and reception.
Timing and control unit
This unit generates all timing and control signals necessary
for the execution of instructions and synchronizes all
internal activities with the clock.
Oscillator
The 8051 has an internal (on-chip) oscillator circuit which
generates the clock pulses by which all internal operations
are synchronized. Normally quartz crystal is used to make
oscillator functional.Typically 12 MHz crystal is used.
PROGRAMMING MODEL OF THE 8051
The programming model of 8051 contains 8 (or 16) bit
registers and memory locations. Each register (or memory
location) has an internal 1byte address with exception of
program counter. Some registers are byte as well as bit
addressable i.e. whole byte of data stored in a register can
be accessed (read/write) at a time or individual bits can be
accessed at a time.
ON-CHIP MEMORY ORGANIZATION
Special function registers (SFRs)
Internal RAM
Internal ROM
Special function registers (SFRs):
Math registers:A and B.
Status register: PSW (Program StatusWord)
Program counter: PC
Pointer registers: DPTR (Data Pointer) and SP (Stack Pointer)
Input output port latches: P0, P1, P2, and P3.
Peripheral data registers:TL0,TH0,TL1,TH1, and SBUF.
Peripheral control registers: IP, IE,TMOD,TCON, SCON, and PCON
Internal RAM
The 8051 has 128 bytes of internal RAM
Register Banks: Bank 0, Bank 1, Bank 2 and Bank 3 (00H to 1FH)
Bit Addressable RAM: Memory locations from addresses 20H to 2FH.
General Purpose RAM: Memory locations from addresses 30H to 7FH.
Internal ROM
The 8051 has 4Kbytes of internal ROM.
It is used to store program instructions to be executed by the microcontroller.
It may also be used to store permanent data like constants, passwords and
lookup tables.
Special function registers (SFRs)
Accumulator:
A
Accumulator is the most useful and versatile register because it is used in
i) all arithmetic operations like addition, subtraction, multiplication and
division.
ii) Majority of logical operations like logical AND, OR, NOT, EX-OR and
Rotate
iii) all data transfer between the 8051 and any external memory.
B
B is used along with A in multiplication operation to hold one of the
operand (either multiplier or multiplicand) and to store higher order byte
of the result. It is also used in division operation to hold divisor and to
store remainder of the result.
PSW
Program status word is an 8 bit register. It is also referred as flag register or
processor status word.
Program status word structure
Program counter: PC
Program counter (PC) is a 16-bit register. It always contains the memory
address of the next instruction to be executed i.e. it points to the instruction
that is to be executed next. As the CPU fetches the op-code (instruction
byte) from the program memory, the PC is incremented automatically point
to the next instruction.
Data Pointer: DPTR
DPTR is a 16 bit register. It is used to point to data byte in external data
(RAM) or program (ROM) memory. It can be used as a single 16 bit register
or can also be accessed as two separate 8 bit registers named DPL and DPH,
where DPH means higher byte of the DPTR and DPL is lower byte of the
DPTR.
Stack pointer: SP
Stack pointer always points to the top of the stack and used to access data
from there. It is an 8 bit register. The data is stored on to the stack using
PUSH and CALL instructions and retrieved using POP and RET instructions.
I/O port registers (latches): P0, P1, P2 and P3.
The 8051 has four 8 bit ports named as P0, P1 P2 and P3, each can be used as an
input or output or both.All ports are byte as well as bit addressable.
Peripheral data registers: TL0,TH0,TL1,TH1, and SBUF.
TL0 (timer 0 lower byte) and TH0 (timer 0 higher byte) together represents a16
bit register for timer 0. They are also used as event counters. Similarly, TL1 and
TH1 are registers for timer 1.
Peripheral control registers: IP,IE,TMOD,TCON, SCON, and PCON.
IP (interrupt priority) is used to assign priorities to different interrupt sources.
IE (interrupt enable) register is used to enable/disable interrupts.
TMOD (timer mode) is used to control behavior i.e. mode of operation of timers.
TCON (timer control) is used to start/stop timers.
SCON (serial port control) register is used to control the modes of operation of
the serial port.
PCON (power mode control) register is used to select power saving modes of
operations.
Internal RAM
The 8051 microcontroller has a total of 128 bytes of internal RAM.
These bytes are assigned addresses 00H to 7FH. These 128 bytes are
grouped into three different areas.
1. Register banks
First 32 bytes from addresses 00H to 1FH are organized as four
banks. Each bank is made up of eight registers named R0 to R7.
2. Bit addressable memory
The 8051 has a bit addressable area of 16 bytes from byte addresses
20H to 2FH in internal RAM, forming a total of 128 (16x8)
addressable bits. An addressable bit can be accessed by its bit
addresses from 00H to 7FH.
3. General Purpose RAM
Bytes from memory locations 30H to 7FH are used for general
purpose data storage.
Internal ROM
The 8051 contains 4Kbytes of internal ROM (on-chip). It occupies
address range from 0000H to 0FFFH. Since it is used to store program
instructions (code), it is also called program memory or code
memory
EXTERNAL MEMORY ORGANIZATION
There are two parallel 64 Kilobytes address spaces
one for the ROM(program memory).
one for the RAM (data memory).
The data space is accessed using external data movement instructions
(MOVX A, source or MOVX destination, A) and code space is accessed using
external code movement instructions (MOVC A, source).
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